? semiconductor components industries, llc, 2001 june, 2001 rev. 8 1 publication order number: mc74hc540a/d mc74hc540a octal 3-state inverting buffer/line driver/line receiver highperformance silicongate cmos the mc74hc540a is identical in pinout to the ls540. the device inputs are compatible with standard cmos outputs. external pullup resistors make them compatible with lsttl outputs. the hc540a is an octal inverting buffer/line driver/line receiver designed to be used with 3state memory address drivers, clock drivers, and other busoriented systems. this device features inputs and outputs on opposite sides of the package and two anded activelow output enables. the hc540a is similar in function to the hc541a, which has noninverting outputs. ? output drive capability: 15 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2 to 6 v ? low input current: 1 a ? high noise immunity characteristic of cmos devices ? in compliance with the jedec standard no. 7a requirements ? chip complexity: 124 fets or 31 equivalent gates figure 1. pinout: 20lead packages (top view) 19 20 18 17 16 15 14 2 1 34567 v cc 13 8 12 9 11 10 oe2 y1 y2 y3 y4 y5 y6 y7 y8 oe1 a1 a2 a3 a4 a5 a6 a7 a8 gnd l l h x l l x h l h x x function table inputs output y oe1 oe2 a h l z z z = high impedance x = don't care soicwide mc74hc540adwr2 device package shipping ordering information mc74hc540an pdip20 1440/box mc74hc540adw soicwide 38/rail 1000/reel tssop20 75/rail tssop20 2500/reel mc74hc540adt mc74hc540adtr2 http://onsemi.com marking diagrams tssop20 dt suffix case 948e hc540a alyw 20 1 so20 dw suffix case 751d 1 20 hc540a awlyyww pdip20 n suffix case 783 1 20 mc74hc540an awlyyww a = assembly location l, wl = wafer lot y, yy = year w, ww = work week
mc74hc540a http://onsemi.com 2 figure 2. logic diagram 18 y1 2 a1 17 y2 3 a2 16 y3 4 a3 15 y4 5 a4 14 y5 6 a5 13 y6 7 a6 12 y7 8 a7 11 y8 9 a8 oe1 oe2 1 19 output enables data inputs inverting outputs pin 20 = v cc pin 10 = gnd
mc74hc540a http://onsemi.com 3 maximum ratings (note 1.) symbol parameter value unit v cc dc supply voltage 0.5 to 7.0 v v i dc input voltage 0.5 to v cc 0.5 v v o dc output voltage (note 2.) 0.5 v o v cc 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 35 ma i o dc output sink current 35 ma i cc dc supply current per supply pin 75 ma i gnd dc ground current per ground pin 75 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance pdip soic tssop 67 96 128 c/w p d power dissipation in still air at 85 c pdip soic tssop 750 500 450 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% 35% ul94vo (0.125 in) v esd esd withstand voltage human body model (note 3.) machine model (note 4.) charged device model (note 5.) 2000 200 1000 v i latchup latchup performance above v cc and below gnd at 85 c (note 6.) 300 ma 1. absolute maximum continuous ratings are those values beyond which damage to the device may occur. extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximumrated conditions is not implied. 2. i o absolute maximum rating must be observed. 3. tested to eia/jesd22a114a. 4. tested to eia/jesd22a115a. 5. tested to jesd22c101a. 6. tested to eia/jesd78. recommended operating conditions symbol parameter min max unit ???? ???? v cc ????????????????????? ????????????????????? dc supply voltage (referenced to gnd) ????? ????? 2.0 ???? ???? 6.0 ??? ??? v ???? ???? v in , v out ????????????????????? ????????????????????? dc input voltage, output voltage (referenced to gnd) ????? ????? 0 ???? ???? v cc ??? ??? v ???? ???? t a ????????????????????? ????????????????????? operating temperature, all package types ????? ????? 55 ???? ???? 125 ??? ??? c ???? ? ?? ? ???? t r , t f ????????????????????? ? ??????????????????? ? ????????????????????? input rise and fall time (figure 3) v cc = 2.0 v v cc = 4.5 v v cc = 6.0 v ????? ? ??? ? ????? 0 0 0 ???? ? ?? ? ???? 1000 500 400 ??? ? ? ? ??? ns 7. unused inputs may not be left open. all inputs must be tied to a high or lowlogic input voltage level.
mc74hc540a http://onsemi.com 4 dc characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter condition v cc v 55 to 25 c 85 c 125 c unit v ih minimum highlevel input voltage v out = 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 v v il maximum lowlevel input voltage v out = v cc 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 v v oh minimum highlevel output voltage v in = v il |i out | 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in = v il |i out | 3.6 ma |i out | 6.0 ma |i out | 7.8 ma 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 v ol maximum lowlevel output voltage v in = v ih |i out | 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih |i out | 3.6 ma |i out | 6.0 ma |i out | 7.8 ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 a i oz maximum threestate leakage current output in high impedance state v in = v il or v ih v out = v cc or gnd 6.0 0.5 5.0 10.0 a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 a 6.0 4 40 160 a 8. information on typical parametric values can be found in the on semic onductor highspeed cmos data book (dl129/d). ac characteristics (c l = 50 pf, input t r = t f = 6 ns) v cc guaranteed limit symbol parameter v cc v 55 to 25 c 85 c 125 c unit t plh , t phl maximum propagation delay, input a to output y (figures 3 and 5) 2.0 3.0 4.5 6.0 80 30 18 15 100 40 23 20 120 55 28 25 ns t plz , t phz maximum propagation delay, output enable to output y (figures 4 and 6) 2.0 3.0 4.5 6.0 110 45 25 21 140 60 31 26 165 75 38 31 ns t pzl , t pzh maximum propagation delay, output enable to output y (figures 4 and 6) 2.0 3.0 4.5 6.0 110 45 25 21 140 60 31 26 165 75 38 31 ns t tlh , t thl maximum output transition time, any output (figures 3 and 5) 2.0 3.0 4.5 6.0 60 22 12 10 75 28 15 13 90 34 18 15 ns c in maximum input capacitance 10 10 10 pf c out maximum threestate output capacitance (output in high impedance state) 15 15 15 pf 9. for propagation delays with loads other than 50 pf, and information on typical parametric values, see the on semic onductor highspeed cmos data book (dl129/d). typical @ 25 c, v cc = 5.0 v, v ee = 0 v c pd power dissipation capacitance (per buffer) (note 10.) 35 pf 10. used to determine the noload dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . for load considerations, see the on semiconductor highspeed cmos data book (dl129/d).
mc74hc540a http://onsemi.com 5 figure 3. switching waveform v cc gnd input a output y t phl oe1 or oe2 50% v cc gnd output y t pzl output y t pzh high impedance v ol v oh high impedance 10% 90% t plz t phz 50% 50% t plh 90% 50% 10% t r t thl t f t tlh figure 4. switching waveform 90% 50% 10% 50% c l * *includes all probe and jig capacitance test point device under test output figure 5. test circuit figure 6. test circuit c l * *includes all probe and jig capacitance test point device under test output 1k w connect to v cc when testing t plz and t pzl . connect to gnd when testing t phz and t pzh . figure 7. logic detail one of eight inverters input a oe1 oe2 output y v cc to 7 other inverters pin descriptions inputs a1, a2, a3, a4, a5, a6, a7, a8 (pins 2, 3, 4, 5, 6, 7, 8, 9) data input pins. data on these pins appear in inverted form on the corresponding y outputs, when the outputs are enabled. controls oe1, oe2 (pins 1, 19) output enables (activelow). when a low voltage is applied to both of these pins, the outputs are enabled and the device functions as an inverter. when a high voltage is applied to either input, the outputs assume the high impedance state. outputs y1, y2, y3, y4, y5, y6, y7, y8 (pins 18, 17, 16, 15, 14, 13, 12, 11) device outputs. depending upon the state of the output enable pins, these outputs are either inverting outputs or highimpedance outputs.
mc74hc540a http://onsemi.com 6 package dimensions so20 dw suffix case 751d05 issue f pdip20 n suffix plastic dip package case 73803 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040 e 1.27 1.77 0.050 0.070 1 11 10 20 a seating plane k n f g d 20 pl t m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition.
mc74hc540a http://onsemi.com 7 package dimensions tssop20 dt suffix case 948e02 issue a dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. 110 11 20 pin 1 ident a b t 0.100 (0.004) c d g h section nn k k1 jj1 n n m f w seating plane v u s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t
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